۱- Introduction

۲- Epitaxial structure and SME-JTE design

۳- Device simulation

۴- Experimental results and discussion

۵- Conclusion

References

Abstract

An edge termination technique, referred to as simple multistep etched junction termination extension (SME-JTE), is presented for 4H-silicon carbide gate turn-off thyristors (4H-SiC GTO). The proposed termination technique can form over ten steps in the termination region with only requiring a few of etching steps. Numerical simulations show that a high termination efficiency over 95% with broad process window for etching depth is obtained for the SME-JTE technique. In addition, a high breakdown voltage of 7500 V has been experimentally demonstrated for the 4H-SiC GTO with 8-step JTE, and which is about 91% of the ideal breakdown voltage for the 50 μm drift layer. The high termination efficiency and simple process of SME-JTE makes it applicable for fabrication of various high-voltage power devices.

Introduction

Silicon carbide (SiC) is considered as a promising material for next-generation power devices due to its unique intrinsic properties such as high electric breakdown field strength, wide bandgap and high thermal conductivity [1, 2]. And the 4H-SiC gate turn-off thyristor (4H-SiC GTO) is of specific interest for pulsed-power applications because of its great advantages over silicon counterparts, such as high-temperature, high-voltage, and high-current applications [3, 4]. Edge termination is a critical technology for power devices. An effective edge-termination technique makes the electric field distribution more uniform at the edge of the device, and which makes the device approach the ideal breakdown voltage capability of the epitaxial layer used. And several specialized edge terminations have been developed to mitigate this effect, including floating guard rings [5], field plates [6], junction termination extensions (JTE) [7-8], and the JTE technique has become one of the preferred methods due to its simple design and high termination efficiency. The JTE technique is usually formed by ion implantation, including multiple-floating-zone JTE, space-modulated JTE and multiple-ring-modulated JTE [9-11]. However, the activation of the implanted dopants is strongly dependent on annealing temperature and time. Moreover, the ion implantation and high temperature annealing process result in crystal damage and surface roughness, which usually affects the performance of power device. Recently, the etched termination has attracted wide attentions because of its simplicity in device design and implantation-free processing. And one of the etched terminations studied in SiC BJT and PiN devices is the single-step JTE, but its BV performance shows high sensitivity to etching depth [12, 13]. Therefore, the multistep JTE formed by etching are developed for wider tolerance of etching step variation [14, 15], and the highest BV of 22kV is achieved with over ten steps JTE in 4H-SiC GTO device [16], but the complexity and cost of device fabrication are significantly increased. In order to realize multistep JTE in a cost-effective way, a method called simple multistep etched JTE (SME-JTE) is proposed in this letter. This method can effectively reduce etching process for realizing multistep JTE, and 16-step JTE only needs 5 etching process. Meanwhile, device simulations and experiments have been carried out to investigate the etching depth variation tolerance and termination efficiency of the SME-JTE technique, broad tolerance for etching depth variation and high termination efficiency have been demonstrated for the 4H-SiC GTO device with SME-JTE technique.