مقاله انگلیسی رایگان در مورد طراحی اتاقک هگزادسیمال افزاینده صرفه جو – الزویر 2021

ABSTRACT

Low power multiplier unit design is one of Digital Signal Processing (DSP) processors’ requirements to meet the growing demands. Though the higher radix Booth multiplier shows the marginal decrease in the power, the generation of hard multiples in the generation unit becomes the bottleneck in implementing the multiplier unit. This paper proposes an energy-efficient radix- 16 Booth multiplier design for combined, signed/unsigned numbers. This paper optimizes the partial product generation unit by (nr – 1) (where n represents input bit size, and r represents radix). As a result, delay and energy reduce significantly. The proposed 16-bit non-pipelined multiplier energy improved by 27.06%, 4.35%, and 27.79%, and the pipelined multiplier is improved by 25.74%, 31.30%, and 28.42%for signed, unsigned, and combined radix-16 designs respectively.

Introduction

In the modern era, with technology scaling, growing components integration and power management on the chip have become major challenges. With the continuous advancement in microprocessor design, to achieve an improved energy utilization for high data encryption rates and transmission. The various compact applications design constraints are satisfied to meet the low power consumption. Among all the units, the multiplier unit is a significant one which decides the average performance of a modern-day processor. Since the multiplier plays a vital role in various applications such as signal/image/video/ processing, it has become an important functional block to be optimized to improve performance [1]. In the day-to-day scenario, a low-power consuming multiplier unit has