I. INTRODUCTION

II. MOTIVATION

III. HEVC INTRA PREDICTION

IV. PROPOSED VLSI ARCHITECTURE

V. IMPLEMENTATION RESULT

VI. CONCLUSION

REFERENCES

In the High Efficiency Video Coding (HEVC), a variety of CU sizes and intra prediction modes significantly improve coding efficiency, but also bring higher computational complexity. This paper proposes a new compact VLSI architecture for HEVC intra prediction, which is geared towards 8K video decoding. It supports all the transform unit (TU) sizes and 35 HEVC intra prediction modes. First, this paper introduces a TU-oriented intra predictor with a throughput of 32 pixels, which can be newly arranged with the TU size. It can be a line of 32 pixels, two lines of 16 pixels, 4 lines of 8 pixels or four lines of four pixels. This TU-oriented architecture allows intra-prediction and inverse discrete cosine transform (IDCT) to be computed in parallel, removing the memory between them. In addition, a horizontal and vertical line buffer for reference sample is proposed, which only cost 0.8K bit and is implemented by register files with SRAM-free. Finally, to further reduce hardware consumption, multipliers can be shared in the prediction. The implementation result shows that the compact architecture supports 8K video application and costs 66.2K logic gates, which is synthesized with the TSMC 65nm process under 400MHz.

INTRODUCTION

The Joint Collaborative Team on Video Coding (JCT-VC) has proposed the latest video coding standard, High Efficiency Video Coding (HEVC) [1]. It can achieve about a 50% bit-rate reduction than the previous video coding standard, H.264/AVC [2], but with higher computational complexity. Like AVC, HEVC also uses block-based coding. Each video frame is divided into multiple CTUs, and each CTU is further divided into smaller CUs. And in HEVC, the CU is further divided into PUs and TUs, where PU is the basic prediction unit and TU is for transform and quantization. The maximum CU size in HEVC is 64×۶۴, not 16×۱۶ in AVC, but the maximum size of TU is only 32 × ۳۲٫ The PU size of intra prediction is suitable for TU, so the largest PU is 32 × ۳۲٫ In addition, the number of HEVC intra prediction modes is 35, not 9 in AVC, in order to describe the texture better [4]. Although the complex block partition scheme and the prediction mode can improve the coding quality, the VLSI implementation is more challenging for high-throughput and high-resolution video coding. Due to the higher complexity and data dependencies, it is difficult to propose a compact high-performance intra prediction architecture. Previously, there was some related work on the intra prediction VLSI architecture, and some were optimized for the reference pixel preparation and prediction process.