مقاله انگلیسی رایگان در مورد پیاده سازی مدل اسپایس TFET برای تجزیه و تحلیل مدار کم توان – IEEE 2016

Abstract

We proposed a compact model for tunneling field effect transistors (TFETs), which combines BSIM4. Our proposed model for tunneling current is based on a drift-diffusion model under the gradual-channel approximation. The total charge for the drain current has been described by a weighted sum of the tunneling charge and the oxide charge for gate-to-source overlap region. In order to obtain TFETs compact model for circuit simulation that operates in every voltage region, the operating current under the various gate-to-source voltage and drain-to-source voltage conditions are considered. Verilog-A description for our proposed model are implemented in the circuit simulator. Model parameters are extracted for conventional TFETs structure by comparing with in-house 2-D TCAD simulation results. After the transistor-level verification, the circuit-level simulation of 81-stage ring-oscillator using our proposed model has been performed.

Introduction

Tunneling field effect transistors (TFETs) are promising device structures for an ultra-low power circuits application [1]–[3]. The tunneling p-n junction in the gate-tosource overlap region leads to the steep subthreshold swing (S.S.) less than 60mV/decade [4]–[6]. Since the fabrication processes of Silicon (Si)-TFETs are compatible with conventional MOSFETs [7], it is expected to be the post Si-CMOS devices for low power technology. However, the circuit characteristics have not been understood yet, because the device structures and the operations of TFETs are different from that of MOSFETs [8]. Therefore, there are still some problems to be solved for the circuit design with TFETs, such as an interactive operation of the pass gate in SRAM [9], a correlation between the circuit operations and the device characteristics such as S.S and the threshold voltage (Vth), the body effect for staked circuits, and the variability in low voltage regime