مشخصات مقاله | |
ترجمه عنوان مقاله | پیاده سازی مدل اسپایس TFET برای تجزیه و تحلیل مدار کم توان |
عنوان انگلیسی مقاله | Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis |
انتشار | مقاله سال 2016 |
تعداد صفحات مقاله انگلیسی | 5 صفحه |
هزینه | دانلود مقاله انگلیسی رایگان میباشد. |
پایگاه داده | نشریه IEEE |
نوع نگارش مقاله |
مقاله پژوهشی (Research article) |
مقاله بیس | این مقاله بیس نمیباشد |
نمایه (index) | scopus – master journals – JCR |
نوع مقاله | ISI |
فرمت مقاله انگلیسی | |
ایمپکت فاکتور(IF) |
2.696 در سال 2017 |
شاخص H_index | 17 در سال 2018 |
شاخص SJR | 1.016 در سال 2018 |
رشته های مرتبط | مهندسی برق |
گرایش های مرتبط | برق الکترونیک – برق قدرت |
نوع ارائه مقاله |
ژورنال |
مجله / کنفرانس | مجله جامعه دستگاه های الکترونی – Journal of the Electron Devices Society |
دانشگاه | Advanced LSI Technology Laboratory, Corporate Research and Development Center, Toshiba Corporation, Kawasaki, Japan |
کلمات کلیدی | SPICE، مدل سازی دستگاه نیمه هادی، ترانزیستورهای اثر میدان |
کلمات کلیدی انگلیسی | SPICE, semiconductor device modeling, field effect transistors |
شناسه دیجیتال – doi |
https://doi.org/10.1109/JEDS.2016.2550606 |
کد محصول | E11646 |
وضعیت ترجمه مقاله | ترجمه آماده این مقاله موجود نمیباشد. میتوانید از طریق دکمه پایین سفارش دهید. |
دانلود رایگان مقاله | دانلود رایگان مقاله انگلیسی |
سفارش ترجمه این مقاله | سفارش ترجمه این مقاله |
فهرست مطالب مقاله: |
Abstract Document Sections I. Introduction II. Device Modeling III. Model Evaluation IV. Conclusion |
بخشی از متن مقاله: |
Abstract We proposed a compact model for tunneling field effect transistors (TFETs), which combines BSIM4. Our proposed model for tunneling current is based on a drift-diffusion model under the gradual-channel approximation. The total charge for the drain current has been described by a weighted sum of the tunneling charge and the oxide charge for gate-to-source overlap region. In order to obtain TFETs compact model for circuit simulation that operates in every voltage region, the operating current under the various gate-to-source voltage and drain-to-source voltage conditions are considered. Verilog-A description for our proposed model are implemented in the circuit simulator. Model parameters are extracted for conventional TFETs structure by comparing with in-house 2-D TCAD simulation results. After the transistor-level verification, the circuit-level simulation of 81-stage ring-oscillator using our proposed model has been performed. Introduction Tunneling field effect transistors (TFETs) are promising device structures for an ultra-low power circuits application [1]–[3]. The tunneling p-n junction in the gate-tosource overlap region leads to the steep subthreshold swing (S.S.) less than 60mV/decade [4]–[6]. Since the fabrication processes of Silicon (Si)-TFETs are compatible with conventional MOSFETs [7], it is expected to be the post Si-CMOS devices for low power technology. However, the circuit characteristics have not been understood yet, because the device structures and the operations of TFETs are different from that of MOSFETs [8]. Therefore, there are still some problems to be solved for the circuit design with TFETs, such as an interactive operation of the pass gate in SRAM [9], a correlation between the circuit operations and the device characteristics such as S.S and the threshold voltage (Vth), the body effect for staked circuits, and the variability in low voltage regime |