Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling mechanism and the corresponding implementations for fixed-point adders and multipliers. We implemented the architecture on Xilinx Virtex-5 XC5VLX110T FPGAs, and the results show that the area and latency overheads are 1% ~ 24% depending on the structure and configuration. This implies the overhead can be minimized if the ALU structure and configuration are chosen carefully for specific applications. As a case study, we apply this architecture to binary cascade iterative refinement (BCIR). 4X speedup is observed in this case study.

In computational science and engineering, users continually seek to solve ever more challenging problems: faster computers with bigger memory capacity enable the analysis of larger systems, finer resolution, and/or the inclusion of additional physics. For the past several decades, standardized floatingpoint representations have enabled more predictable numeric behavior and portability, but at the expense of making it impractical for users to exploit customized precision with good performance. The introduction of reconfigurable computing platforms provides scientists with an affordable accelerating solution that not only has the computational power of dedicated hardware processors (ASICs and DSPs), but also the flexibility of software due to the fabric and circuit configurability [13].