مقاله انگلیسی رایگان در مورد افزایش دقت بلند مدت شبکه عصبی باینری مبنی بر آرایه ممریستور – MDPI 2022

Abstract

Introduction

Experiment

Results

Discussion

Conclusions

References

Abstract

     In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system’s operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 105 s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications.

Introduction

     Energy is a crucial resource for smart devices in the Internet of Things (IoT), as most applications are powered by batteries or use energy-harvesting techniques [1–4]. Because of this, energy-efficient artificial intelligence technologies are becoming increasingly important for the IoT. Since Deep Neural Networks (DNNs) require a high bandwidth, large memory capacity, and large power consumption, running DNNs on target embedded systems and mobile devices has become a challenge [5–10]. In comparison, Binarized Neural Networks (BNN) can significantly reduce computational complexity and memory consumption while having satisfactory accuracy on various image datasets [11]. In embedded IoT systems, neural networks must be able to perform pre-trained cognitive tasks in an efficient way. In this case, the weights of the trained neural network should remain unchanged and only limited in-field updates should be performed. Currently, the resource consumption by add-ons has become a limitation in memristor-based analog computing in memory systems. Analog designs require additional circuits, such as analog-to-digital and digital-to-analog converters, to fight against undesirable device properties.

Results

     Electrical tests were performed in the previously fabricated 3D VRRAM arrays. Figure 1d shows the I–V curves of the device with the Ti interfacial layer (DWT) and without the Ti interfacial layer (DOT). Both devices exhibit typical bipolar characteristics. The parameters are clearly defined in Figure 1d. The DOT switched from an LCS to an HCS when a voltage of +6V was applied to the TE. However, this programming voltage was decreased to +5V for the DWT when an interfacial layer was used. To ensure that the resistance state of the device was not affected, the read voltages for the DOT and the DWT were chosen to be 2 V and 1.5 V, respectively. The on/off ratios collected from 20 different devices are shown in Figure 1e. It can be seen that the on/off ratio for the DWT was 1 order higher than that of the DOT, primarily due to the increased resistance of the low-resistance state, which is consistent with the I–V characteristics in Figure 1d. The nonlinear ratio (NR) is defined as the ratio of the currents at Vread and 1/2Vread. As shown in Figure 1e, the NR for the DOT was calculated from the currents at 2 V and 1 V, while for DWT, the NR was calculated at 1.5 V and 0.75 V. The nonlinearity of the DWT device was smaller than that of the DOT device. Therefore, the integration scale will be sacrificed when the SSD is integrated into a 3D architecture.