Abstract

I. Introduction

II. Three-Level Neutral Point Clamped Inverters

III. Proposed Neutral Point Clamped Inverters

IV. Operation of the Proposed Three-Level NPC Inverter

V. Comparison of the Proposed and Conventional Inverters

VI. Experimental Results

VII. Conclusion

References

Abstract

     The traditional neutral point clamped (NPC) inverter has short-circuit problem. The risk of short-circuit can be decreased by using dead-time in the switching signals. However, the dead-time decreases the achievable output voltage and causes distortion in the waveforms. To overcome the short-circuit problem, dual-buck NPC (DB-NPC) and split-inductor NPC (SI-NPC) inverters have been researched. However, the voltage stress of the two external diodes in the DB-NPC inverter is higher. On the other hand, the SI-NPC inverter has a problem of generating huge voltage spikes in the dead-time, which can destroy the semiconductor devices. In addition, the SI-NPC inverter cannot provide reactive power. This article presents a family of NPC inverters consisting of single-phase, three-phase, and cascaded inverters. The proposed inverters have no short-circuit and dead-time issues, therefore no high voltage and current spikes are caused. Also, the dead-time in the switching signals can be minimized. As a result, the magnitude of the output waveforms can be increased, and quality can be improved. Unlike the DB-NPC inverter, the voltage stress of all the semiconductor in the proposed inverter is lower, and unlike the SI-NPC inverter the proposed inverter provides reactive power. In this article, the proposed three-level NPC inverter is analyzed, designed, and tested. The voltage stress of the semiconductor devices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two external diodes is the source voltage. In addition to the aforementioned benefits, the proposed cascaded inverter reduces the total number of inductors. To verify the analysis, detailed simulation, and experimental results of the proposed three-level inverter with input voltage 640 V, output power 1.2 kW, and output voltage 220 Vrms are provided.

Introduction

     T HE traditional H-bridge inverter is shown in Fig. 1. The voltage stress on its switches is the input voltage Vdc. Therefore, the H-bridge inverter is well suitable for low-voltage applications. In high-voltage applications [1] such as HVdc transmission [2], large motor drive [3], locomotive [4], solid-state transformers [5], and reactive power compensation [6], the multilevel inverters are preferred. Flying capacitor [7], neutral point clamped (NPC) [8], and cascaded inverters [9], [10] are the famous multilevel inverter topologies.

     The flying capacitor inverters synthesize output voltage by adding voltages of the flying and dc-link capacitors. The NPC inverters synthesize output voltage by adding voltages of the dc-link capacitors. The cascaded inverters synthesize output voltage by adding voltages of the series-connected H-bridge cells. The cascaded inverters are highly modular and can reach a higher output voltage [11]. Also, they can bypass faulty cells [12]. The multilevel inverters have the advantages of lower switch voltage stress, lower switching losses, smaller output filter, better output waveforms, and lower electromagnetic interference (EMI) noise issues.

     The multilevel inverters are also getting popular in lowvoltage and low-power applications due to the possibility of obtaining lower common-mode voltage and higher efficiency over the H-bridge inverter. In [13], multilevel inverters have been discussed for the photovoltaic (PV) systems. In [14], a half-bridge three-level NPC inverter is compared with a halfbridge two-level inverter for PV applications. It is found in [14] that a lower leakage current and higher efficiency can be realized with the NPC inverter.

Conclusion

     This article presented new types of single-phase, three-phase, and cascaded NPC inverters. The proposed inverters have no short-circuit risk. The dead-time in the switching signals can be reduced. As a result, the distortion in the output waveforms can be decreased, higher switching frequencies can be used for the passive components size reduction and maximum available output voltage gain can be reached. Unlike the conventional SI-NPC inverters, the proposed inverters do not generate high-voltage spikes in the dead-time and provide reactive power. Unlike the DB-NPC inverters, the voltage stress of all the external diodes in the proposed inverter is lower. The proposed cascaded inverter inherits all the features of the proposed three-level inverter. In addition, it reduces the number of inductors by sharing the inductors between the cascaded units.

     A 1.2-kW hardware prototype was fabricated and tested with various loads at the input voltage 640 V, output voltage 110/220 Vrms, output power 1.2 kW, line-frequency 60 Hz, and switching frequency 30 kHz. The experimental results verified that the proposed inverter could generate good output waveforms, provide reactive power, works with dead and overlap-times, and obtains higher efficiency.