مقاله انگلیسی رایگان در مورد تحمل خطا در سیستم های محاسباتی عصبی – الزویر 2020

1- Introduction

2- Preliminaries

3- Fault tolerant framework for NCS

4- Experimental results

5- Conclusion

References

Abstract

In recent years, neuromorphic computing systems (NCS) based on memristive crossbar have provided a promising solution to enable acceleration of neural networks. However, Stuck-at faults in the memristor devices significantly degrade the computing accuracy of NCS. In this paper, we propose an effective fault tolerant framework for memristive crossbar-based neuromorphic computing systems. First, a fault tolerance-aware hierarchical clustering method is proposed to partition weight connections of a sparse neural network into clusters. Then, for each cluster, memristive crossbar configuration is proposed to determine a suitable size of the crossbar with consideration of both hardware cost and successful mapping rate. Next, an integer linear programming formulation is developed to derive a connection-memristor mapping for fault tolerance. Finally, an efficient matching-based heuristic algorithm is further proposed to speed-up the fault-tolerant mapping process. Experimental results show that the proposed fault tolerant framework can improve the successful mapping rate and simultaneously reduce the hardware cost.

Introduction

Neuromorphic computing systems (NCS) based on hardware designs intend to mimic neuro-biological architectures [1]. Different from conventional von Neumann architectures, NCS is often constructed with highly parallel, extensively connected, and collocated computing and storage units, which eliminates the gap between CPU computing capacity and memory bandwidth [2]. However, the implementation of NCS on CMOS technology has been shown to suffer from mismatch between NCS building blocks (neuron and synapse) and CMOS primitives (Boolean logic). To address this problem, the emerging memristive technology is adopted to implement synapse circuit due to the similarity between memristive and synaptic behaviors [3,4]. For example, the memristor is suitable to store the weight of synapse since the resistance of memristor can be programmed by applying current or voltage. In addition, compared with the stateof-the-art CMOS design, memristive crossbar has been proven as one of the most efficient nanostructures that carry out matrix-vector multiplications while hardware cost and computation energy are significantly reduced [1]. However, despite of these tremendous advantages, NCS implementations on memristive crossbars also encounter some design challenges.