INTRODUCTION

HIGH-SPEED analog-to-digital converters (ADCs) with around 6-bit resolution have been used for oscilloscopes and the read channels of data-storage devices (such as HDDs and DVD drives) since the 1990s [1], [2]. Currently, such ADCs are used in Ethernet, electrical wire-line links, and optical communication systems [3]. Flash ADCs are traditionally used for these applications because of their high operation speed. However, flash ADCs have a drawback: their area and power consumption increase exponentially with the resolution [4]. In addition, because the number of the comparators increases, the input capacitance of the ADC becomes larger, and this often restricts performance [5]. A time-interleaved successive approximation register (SAR) architecture have been used to address these issues and attain conversion speeds of several tens of GS/s [6]. However, although an SAR ADC has high power efficiency, the overall performance deteriorates as the number of time-interleaved channels grows, because the clock delivery needs to cover a larger area and clock timing accuracy becomes critical at a high conversion rate. Subranging architectures have coarse and fine decisions wherein the conversion range of the fine decision is determined according to the coarse decision result. This architecture potentially gives a conversion speed, area, and power that are roughly half way between those of flash ADC and SAR ADC. The subranging architecture can thus minimize the problems that arise from the large area of time-interleaved SAR ADCs [6]. To achieve this end, several issues should be addressed. One is that the conversion speed and resolution are limited by the settling time of the reference voltages, because the conventional subranging architecture uses reference resistor ladders to generate various threshold voltages for the coarse and fine decisions. Additionally, the use of different samplers for the coarse and fine decisions [4] causes sampling errors between decisions. Since the sampling errors cannot be compensated for by calibrating the comparators, redundant comparators are needed [7]. To solve these problems, this paper proposes a scheme in which the reference voltages for coarse and fine decisions are generated without using resistive ladders. The proposed scheme eliminates the sampling error by using the same CDACs to capture the input signal for both decisions. In addition, a calibration technique is used to reduce the error caused by the offset voltages of comparators. These measures enable the use of the same comparators for both decisions without any redundant comparators and further reduce the ADC area. Section II of this paper explains the design issues concerning the conventional subranging architecture and the proposed interpolated subranging ADC. Section III describes the circuit implementation of a 6-bit ADC and its calibration method. The results of the measurement of a test chip are presented in Section IV. Section V presents the conclusion.