۱- Introduction

۲- Experimental details

۳- Results and discussion

۴- Conclusion

References

Abstract

A strategy of reducing the power consumption to cure gate dielectric damage by electrothermal annealing (ETA) is proposed. A tri-gate FinFET was fabricated to demonstrate the damage curing by the ETA. Localized Joule heat induced by high current flowing through dual gate electrodes successfully annealed the damaged gate dielectric. Furthermore, a design methodology to save power consumption during the ETA was explored. Electrical measurements and simulations were performed considering scaling-down and material engineering points of view. This work contributes to improving the reliability of the FinFET by developing the ETA approach with reduced power consumption.

Introduction

The tri-gate FinFET has been widely used in logic circuits because of its enhanced gate-to-channel controllability and immunity against short-channel effects (SCEs) [1]. However, during iterative device operation, aging of the gate dielectric by hot-carrier injection (HCI) or Fowler-Nordheim (FN) stress is inevitable. Typically, the gate dielectric damage causes reliability issues such as degradation of subthreshold slope (SS), a shift in threshold voltage (VT), and decrement of the ONstate current (ION) [2]. To cure the abovementioned gate dielectric damage, wafer scale annealing, such as forming gas annealing (FGA) and deuterium (D2) annealing under hydrogen and deuterium gas ambient has been widely used [3,4]. However, such approaches require long curing times and bulky as well as expensive equipment, such as a furnace. Most importantly, the conventional wafer scale annealing cannot be applied to a packaged chip because it can lead to the melting and decomposition of the metal interconnections. To overcome these limitations of conventional annealing, an electrothermal annealing (ETA) method has been suggested which uses Joule heat generated by the high current flowing in the device itself to cure the damaged gate dielectric [5]. Compared to conventional FGA or D2 annealing, the ETA has a faster annealing speed (< 1 s), lower thermal budget, and excellent annealing selectivity. However, despite these advantages, the ETA can be a concern in terms of power consumption because the fundamental mechanism of the process involves high current density through the conducting materials. For instance, in prior studies, 12 mW was used to cure the damaged gate dielectrics of flash memory and 3.2 mW was consumed to repair radiation damage [5,6]. From an energy efficiency point of view, the ETA power consumption should be reduced, however, few such attempt have been made. In this work, we demonstrate a strategy of low power consumption ETA to anneal the damaged dielectric of a tri-gate FinFET, fabricated on a silicon-on-oxide (SOI) substrate. The results are characterized by electrical measurements. In addition, a supportive simulation study was performed with the aid of a 3-dimensional thermal simulator (COMSOL) to investigate the effect of design parameters such as device dimension and structural material, to construct a FET which further reduces the power consumption needed for the ETA [7]. First, the effect of representative geometric device dimensions such as gate length (LG), fin width (WFin), oxide thickness (tOX), buried oxide thickness (tBOX), and substrate thickness (tSub) were analyzed. Second, the reduction in power consumption based on the underlying substrate material and gate material was examined.