Most of the existing artificial neural networks (ANNs) applications, particularly for commercial environment, are developed as software. Yet, the parallelism offered by hardware may deliver some advantages such as higher speed, reduced cost, and higher tolerance of faults (graceful degradation) [1, 2]. Among various developed methods of ANNs implementations in field programmable gate arrays (FPGAs), e.g., [3 – 6], there is a breed of implementation which allows the structure of the ANN (i.e., the number of layers and/or neurons, etc.) to be altered without the need of re-synthesizing and re-implementation of the whole FPGA project. This feature increases the ANNs implementation flexibility to the similar level as offered by software, at the same time maintaining the advantages delivered by hardware. Unfortunately, existing solutions, e.g., [7 – 9], are based on fixed point arithmetic, have strongly limited calculations accuracy of the activation function, and require dedicated software tools for the formulation of a set of user instructions controlling the ANN calculations in the developed hardware. Some of them [9, 10] do not employ parallel architecture exploiting only a single neuron block for the calculations of the whole ANN. In the case of [10] floating point (FP) arithmetic is used and a relatively high accuracy of the activation function is achieved, however the feasibility of the alteration of the ANN structure without reimplementation of the whole project is heavily compromised. In this brief paper the FPGA implementations of feed forward ANNs, namely the resource-saving and parallel, are presented. The resource-saving implementation characterizes considerably lower calculations speed than the parallel one, but requires remarkably lower number of FPGA resources. Both implementations employ single precision floating point arithmetic and apply a very high accuracy algorithm for the activation function calculation with the Padé approximation of the exponential function. This enables the direct exploitations of the ANN’s weights and biases values calculated off-line, e.g., by the Matlab software. The important feature of the proposed implementations is that the structure of the ANN can easily be changed (even on-line during the system operation) by the replacement of the FPGA Block RAM memory content without the usage of FPGA synthesis tools. The aforementioned traits of the developed implementations make them a solid and versatile candidate for a hardware accelerator of ANNs calculations. Particularly, the Padé approximation of the exponential function as well as the usage of the block RAM memory for the ANN’s structure definition also constitute a novelty of the proposed solution.