مقاله انگلیسی رایگان در مورد کدگذاری قطبی بررسی توازن – IEEE 2019

Parity-check (PC) polar codes can yield better error-correcting performance compared with the cyclic redundancy check (CRC) aided polar codes under successive cancellation list decoder. However, PC bits are incapable of detecting error as effective as CRC. To overcome this shortage, this paper proposes a scheme of CRC-aided PC polar codes. The proposed scheme can detect error before decoding is completed and outperform the standard CRC-assisted polar codes with better capability of error detecting.

Introduction

POLAR codes, introduced by [1], have been adopted in the 5 th generation wireless communication standard as the control channel coding scheme for the enhanced Mobile Broadband (eMBB) service. Currently, the most dominant decoding scheme for polar codes is the cyclic redundancy check (CRC) assisted successive cancellation list (CA-SCL) algorithm [2], [3] which enables polar codes to be competitive with state-of-the-art codes. To further improve the performance of CA-SCL at high signal noise ratio (SNR), some research was conducted based on the CRC code design. Zhang et al. searched the optimal CRC polynomials for the standard CA-SCL decoder to eliminate the erroneous polar codewords with minimum Hamming weight (MHW) in decoding [4]. Using the same idea, [5] and [6] respectively designed the protected bits of CRC and the locations of CRC bits. However, all the above schemes have two drawbacks. First, they cannot detect error in the intermediate decoding process.1 Second, they cannot correct the decoding error. To solve the first problem, [7] first proposed a multiCRC polar codes which can also reduce the decoding delay and memory space. Meanwhile, another partitioning method which can reduce the memory requirements associated with SCL decoding was proposed by [8]. Considering these structures suffer from performance degradation, [9] proposed an optimized scheme. However, its designing complexity is high and it fails to give a universal concatenation scheme. The second defect can be addressed by parity-check (PC) polar coding which is first proposed by [10]. After that, [11] designed the PC coding based on the polar kernel to improve the performance. Especially, [12] used a single cycle shift register (CSR) to design a PC polar coding scheme, which has been verified to provide significant performance gain.