I- Introduction

II- Design of Analog and Digital Hybrid MAC Circuit

III- Experimental Results

IV- Conclusions

REFERENCES

Abstract

Demand for high-performance hardware acceleration for machine learning applications is increasing rapidly. This paper presents a low power analog and digital hybrid MAC (Multiply and Accumulation) circuit for artificial neural networks. The proposed MAC circuit consists of an analog synapse unit, digital preprocessing and postprocessing unit for support of the parallel analog synapse cores. As the hybrid MAC circuit supports relatively low power and fast multiple MAC operations, it provides a good advantage in developing hardware accelerator for artificial neural networks.

INTRODUCTION

Deep Neural Network (DNN) technology is rapidly evolving on the basis of the Internet which enables acquiring large amounts of learning data and hardware technology capable of high-speed parallel processing. In recent years, various Deep Neural Network (DNN) frameworks have been proposed such as R-CNN, SSD and YOLO V2, etc. Since the convolution operation is composed of millions of multiplications and additions, a high-performance accelerator having a parallel structure is required for real-time image recognition. The purpose of this study is to design a new MAC circuit that can be efficiently used in DNN for an image recognition field which is one of the most popular application fields of artificial neural networks. This paper is organized as follows. Section II presents the proposed MAC algorithm and the architecture of our hybrid MAC circuit. Synthesis results are given in Section III. Section IV presents the conclusions.