This work is devoted to the study of application of new topologies in the design of networks-on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC design, and it is developed an optimized routing algorithm with the decreased memory usage. The proposed routing algorithm was compared with Table routing, Clockwise routing, and Adaptive routing algorithms, previously developed for ring circulant topologies, and specialized routing algorithm for multiplicative circulants. The results of synthesis of routers implementing proposed routing algorithms are presented. The cost of ALM and register resources for the implementation of communication subsystems in NoCs with circulant topologies is estimated.

Introduction

Multiprocessor systems-on-chip (MPSoCs) [1] are currently one of the fastest growing areas in computing. An extensive increase in the size of the chip and the number of transistors per unit area allows developing chips with tens and hundreds of processor cores even now. At the same time, the problem of effective organization of a communication subsystem that would ensure quick data exchange between nodes of such NoCs is becoming urgent [2]. Since communication is carried out within the framework of a single chip, laws and principles that exist in telecommunication networks work differently in NoCs; therefore, the development of new solutions and methods for organizing data transfer in such networks is required. In particular, it is the topology that has a significant impact on NoC performance. The most common are classical regular topologies such as mesh [3] and torus [4], which do not always meet modern requirements for NoCs, especially with an increase in the number of nodes [5]. Different researchers suggest other topology options among which we can distinguish hypercube [6, 7, 8], chordal ring [9, 10], spidergon [11], L-networks [12]. Their feature is that they can be reduced to presentation in the form of ring-like graphs called circulant topologies in the general form. Optimal circulants have several significant advantages over mesh and torus topologies – better structural survivability, reliability, and connectivity [13, 14].

I. INTRODUCTION

II. ON-CHIP-ANTENNAS AND APPLICATION AREAS: CURRENT STATE-OF-THE-ART

III. ON-CHIP-ANTENNAS AND EMERGING APPLICATIONS: POTENTIALS, CHALLENGES, MITIGATION TECHNIQUES, AND FUTURE PROSPECTS

IV. CONCLUSION

REFERENCES

The ever-growing demand for low power, high performance, cost-effective, low-profile, and highly integrated wireless systems for emerging applications has triggered the need for the enormous innovations in wireless transceiver systems, components, architectures and technologies. This is especially valid for the antenna which is an integral component of the wireless transceiver systems and contributes significantly in determining their overall performance. Antenna-on-Chip (AoC) is an alternative antenna technology, which has drawn a substantial attention in recent days because of its various benefits over off-chip antenna technology. A few of these benefits include miniaturization, low power, low cost, and high integration of the wireless modules. Motivated by these valuable advantages and to unveil the true potential of the AoCs, this article presents, for the first time, a comprehensive survey of the suitability, advantages, and challenges of the AoCs for the emerging wireless applications such as 5th generation (5G) Wireless Systems, Internet-of-Things (IoT) Wireless Devices and Systems, Wireless Sensor Networks (WSNs), Wireless Interconnects, Wireless Energy Transfer, Radio Frequency (RF) Energy Harvesting, Biomedical Implants, Unmanned Aerial Vehicles (UAVs), Autonomous vehicles, Innovative characterization methods for Integrated Circuits (ICs) and Antennas, and Smart City. In addition, this article presents the current stateof-the-art of the AoC’s applications by classifying their applications in Millimeter-Wave (MM-Wave) band, Terahertz (THz) band, and low-frequency bands. The article also investigates and describes some useful methods for the mitigation of the challenges and issues posed by the emerging applications for the realization of the AoCs in a systematic manner. A concise description of the future directions of the AoCs with respect to each emerging application is also a part of this article. It is expected that this well-structured and organized survey will not only act as an excellent source of scholarship for the relevant research community, but also open up a world of novel research opportunities.

INTRODUCTION

The last decade has witnessed an explosive advancement in the design of low-profile, power-efficient and cost-effective transceivers for wireless applications. Besides tremendous developments in ICs, transistor scaling and fabrication processes [1]–[3], this progress is essentially credited to the efficient integration and packaging methods [1]. The role of such integration methods is expected to proliferate in the future, because of the emergence of innovative applications such as 5G wireless technology [4]–[14], IoT wireless devices and systems [15], WSNs [16]–[20], and Smart Cities [21], [22], etc. Recently, System-on-Chip (SoC) integration technique has drawn an ample attention to the wireless applications over the alternative integration methods, i.e. Multichip module and System-in-Packaging (SiP) owing to its multitude of valuable benefits. A few of these advantages include low cost, miniaturization, low power consumption and less complexity for the wireless modules. All the sections (digital, Analog-to-Digital Converter (ADC)/Digital-to-Analog Converter (DAC), RF front-end, and antennas) of a modern SoC based wireless system are placed on the same substrate as shown in Figure 1. The antenna of such a system is called as On-Chip-Antenna (AoC).

Abstract

This paper presents a reconfigurable fault tolerant routing for Networks-on-Chip organized into hierarchical units. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16 × 16 network show a speedup by a factor of almost four for routing reconfiguration compared to the state-of-the-art approach. Evaluation with transient faults shows that a dedicated reconfiguration unit enables successful reconfiguration of routing tables even in case of high error probabilities.

Introduction

The ongoing technology scaling allows an increasing number of cores to be implemented on a single chip, e.g. Intel’s Xeon Phi Coprocessor [1] or Tilera’s Tile-MX multicore processor [2]. As this scaling trend continues [3], future multiprocessor systems will feature hundreds of cores on a single chip.

The increasing size of on-chip systems poses a new challenge to Networks-on-Chip (NoCs).Mechanisms implemented in an NoC, such as table-based routing, work well for small systems but do not scale for bigger systems. A possibility to cope with scalability problems is the introduction of a hierarchical structure to NoCs. A hierarchical NoC can be obtained by constructing its topology using subnetworks or by segmenting a given topology into logical units. Both subnetworks and logical units enable formerly global mechanisms to be applied locally thus reducing their complexity. Compared to subnetworks, logical units have the advantage that they can be applied without changing an existing topology. Typically, network nodes (switch + core) are grouped into a logical unit if they are part of the same task and share a spatial relation.

The downside of technology scaling is the increased probability of occurrence of permanent faults in an NoC due to manufacturing inaccuracies [4] or wear-out effects such as electromigration [5] that emerge during system operation. The failure of links or switches due to permanent faults results in an altered network topology. In such a case, static routing can no longer maintain connectivity between system components. For this reason, it is crucial that the routing is adapted to the new network situation to enable packets to circumvent faulty components.