مقاله انگلیسی رایگان در مورد مدارهای دیجیتال و آنالوگ TFET – الزویر ۲۰۱۸

elsevier

 

مشخصات مقاله
ترجمه عنوان مقاله مدارهای دیجیتال و آنالوگ TFET: طراحی و کارایی
عنوان انگلیسی مقاله Digital and analog TFET circuits: Design and benchmark
انتشار مقاله سال ۲۰۱۸
تعداد صفحات مقاله انگلیسی ۱۶ صفحه
هزینه دانلود مقاله انگلیسی رایگان میباشد.
پایگاه داده نشریه الزویر
نوع نگارش مقاله
مقاله مروری (Review Article)
مقاله بیس این مقاله بیس میباشد
نمایه (index) Scopus – Master Journal List – JCR
نوع مقاله ISI
فرمت مقاله انگلیسی  PDF
ایمپکت فاکتور(IF)
۱٫۷۹۳ در سال ۲۰۱۷
شاخص H_index ۸۲ در سال ۲۰۱۹
شاخص SJR ۰٫۴۹۲ در سال ۲۰۱۷
شناسه ISSN ۰۰۳۸-۱۱۰۱
شاخص Quartile (چارک) Q2 در سال ۲۰۱۷
رشته های مرتبط مهندسی برق
گرایش های مرتبط مهندسی الکترونیک، مدارهای مجتمع الکترونیک، الکترونیک قدرت
نوع ارائه مقاله
ژورنال
مجله الکترونیک حالت جامد – Solid-State Electronics
دانشگاه  DPIA, Università degli Studi di Udine, Via delle Scienze 206, I-33100 Udine, UD, Italy
کلمات کلیدی تونل ترانزیستورهای اثر میدان، TCAD، شبیه سازی، مدارهای دیجیتال، مدارهای آنالوگ
کلمات کلیدی انگلیسی Tunnel-FET، TCAD، Simulation، Digital circuits، Analog circuits
شناسه دیجیتال – doi
https://doi.org/10.1016/j.sse.2018.05.003
کد محصول  E11079
وضعیت ترجمه مقاله  ترجمه آماده این مقاله موجود نمیباشد. میتوانید از طریق دکمه پایین سفارش دهید.
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فهرست مطالب مقاله:
Abstract

۱- Introduction

۲- Virtual technology platforms and methodology for simulation and benchmarking

۳- Analysis of digital circuits

۴- Analog/mixed-signal applications

۵- Conclusions

References

بخشی از متن مقاله:

Abstract

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

Introduction

After the initial report in [1], complementary-metal-oxide-semiconductor (CMOS) transistors based on band-to-band-tunneling (BtBT), usually referred to as Tunnel-FETs (TFETs), have been extensively explored as possible replacements of, or complements to, conventional MOSFETs for low-power/low-energy electronic circuits targeting a supply voltage VDD below 0.5 V [2–۵]. TFETs embody a promising small slope FET concept able to achieve a subthreshold swing (SS) below the 60 mV/dec room temperature limit of conventional MOSFETs, as demonstrated by many theoretical works based on simulations (see [5] and references therein), and by some recent encouraging experimental results [6,7]. The lower SS compared to a conventional MOSFET can be exploited in two ways: if the threshold voltage is the same as in the MOSFET, the TFET will have a lower off-current (and thus lower static energy dissipation); if instead the same off-current is set in both devices, the TFET will be able to deliver a similar on-current as the MOSFET at a lower supply voltage VDD, thus reducing both static and dynamic energy dissipations (which are proportional to VDD and VDD2 , respectively). In this respect, circuit simulations have attributed to TFETs the potential to outperform conventional MOSFETs in the ultralow voltage domain (VDD < 0.4 V) in both analog [8–۱۰] and digital [11–۱۷] applications. At higher supply voltages, however, the drive current of TFETs is significantly lower than the one of conventional MOSFETs. It is thus clear that TFETs can outperform MOSFETs only if they can deliver an SS significantly smaller than 60 mV/dec over a large current range in the subthreshold region. In many experiments this target has not been achieved, which may be due to fundamental as well as to material and device design issues [18–۲۴]. As a result, the performance of the fabricated TFETs lags behind the optimistic figures reported in simulation studies, but experimental results have been steadily improving along the years. Another intrinsic advantage of TFETs over conventional MOSFETs stems from the lower temperature dependence of BtBT compared to thermionic emission [56], which may directly translate in less temperature sensitivity of TFET circuits. This has not been observed in early experimental reports about TFETs mainly because the conduction at very low current levels was often dominated by Trap-Assisted-Tunneling (TAT) and Shockley-Read-Hall (SRH) recombination processes [25]. Nevertheless, the fabrication process for TFETs is also getting more and more controlled and encouraging variability analysis are being reported both for statistically meaningful experimental samples [26], and for simulation based studies [27,28].

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