مقاله انگلیسی رایگان در مورد تجزیه و تحلیل قابلیت اطمینان گسترده کنترلر ربات مبتنی بر تحمل پذیری خطا – ۲۰۱۹ IEEE

مقاله انگلیسی رایگان در مورد تجزیه و تحلیل قابلیت اطمینان گسترده کنترلر ربات مبتنی بر تحمل پذیری خطا – ۲۰۱۹ IEEE

 

مشخصات مقاله
ترجمه عنوان مقاله تجزیه و تحلیل قابلیت اطمینان گسترده کنترلر ربات مبتنی بر تحمل پذیری خطای مدار مجتمع دیجیتال برنامه پذیر
عنوان انگلیسی مقاله Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller
انتشار مقاله سال ۲۰۱۹
تعداد صفحات مقاله انگلیسی ۴ صفحه
هزینه دانلود مقاله انگلیسی رایگان میباشد.
پایگاه داده نشریه IEEE
مقاله بیس این مقاله بیس نمیباشد
نوع مقاله ISI
فرمت مقاله انگلیسی  PDF
شناسه ISSN ۲۳۷۳-۰۸۶۲
مدل مفهومی ندارد
پرسشنامه ندارد
متغیر دارد
رفرنس دارد
رشته های مرتبط برق، کامپیوتر
گرایش های مرتبط هوش مصنوعی، مهندسی نرم افزار، الکترونیک، مدارهای مجتمع الکترونیک، برنامه نویسی کامپیوتر، مهندسی کنترل، ماشین های الکتریکی
نوع ارائه مقاله
کنفرانس
کنفرانس Latin American Test Symposium
دانشگاه Faculty of Information Technology, Brno University of Technology, Centre of Excellence IT4Innovations, Brno, 612 66, Czech Republic
کلمات کلیدی تجزیه و تحلیل قابلیت اطمینان، TMR، مدار مجتمع دیجیتال برنامه پذیر، تحمل پذیری خطا، کنترلر ربات
کلمات کلیدی انگلیسی Reliability Analysis، TMR، FPGA، Fault Tolerance، Robot Controller
شناسه دیجیتال – doi
https://doi.org/10.1109/LATW.2019.8704554
کد محصول E13312
وضعیت ترجمه مقاله  ترجمه آماده این مقاله موجود نمیباشد. میتوانید از طریق دکمه پایین سفارش دهید.
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فهرست مطالب مقاله:
Abstract

I- Introduction

II- Reliability Analysis and its Improvement

III- Evaluation Platform and Experimental System

IV- Reliability Analysis and Experimental Evaluation

V- Conclusions and Future Research

References

 

بخشی از متن مقاله:

Abstract

The reliability of safety-critical systems is very important especially in case of electronic systems which are working in environment with increased occurrence of faults. As an example, space, aerospace or medical systems can serve. Fault tolerance is one of the techniques the goal of which is to avoid the impact of faults on such systems. Lots of fault tolerance techniques exists and new ones are under investigation. This paper is targeted mainly to Field Programmable Gate Arrays (FPGAs) which are also the target technology of many fault tolerant techniques. It is important to evaluate and test these techniques. This paper is the continuation of our previously published research results which presents experimental approach to evaluate such fault tolerance techniques by monitoring the impact of faults in the experimental electro-mechanical system utilizing robot navigation in a maze. However, in this paper, we research and compare similarities of the theoretical estimation to various methods of the SEU injection approaches. The theoretical estimation is calculated using known equations. The impact of artificially faults injected into the electronic controller, in which Triple Modular Redundancy is applied, is monitored and used for statistic reliability analysis. This approach serves as a tool for the fast reliability evaluation during the development process of fault tolerance systems.

INTRODUCTION

The reliability of safety-critical electronic systems which are working in environment with increased occurrence of faults is a very challenging topic. A technique called fault tolerance [1] is commonly used technique which makes electronic systems more reliable. The goal of this approach is to keep the system functional, even in the presence of faults. It means that fault tolerance accepts the fact a fault can appear in electronic system. Various types of redundancy are the core of such techniques. Hardware and time redundancy are the most common ones. Combination and improvements of these basic methods are still under investigation, e.g. authors of [2] present approach which is based on the combination of hardware and time redundancies. Many fault-tolerant methodologies targeted to Field Programmable Gate Arrays (FPGAs) have been developed and new ones are under investigation [3]. The main reason is that FPGAs are more popular thanks to their flexibility and ability to be reconfigured in case of fault occurrence. Sensitivity of FPGAs to faults caused by charged particles [4] is the problem from the reliability point of view. The configuration of FPGA is stored as a bitstream in SRAM memory and charged particle can cause inversion of bit in the bitstream. This event is called Single Event Upset (SEU) [5].

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