The high-redundancy actuator (HRA) is a linear displacement actuation system, which consists of a large number of small electromechanical actuation elements arranged in a series and parallel configuration. The performance of a HRA with 9 direct-driven linear electromechanical actuators was analyzed under different fault conditions with the aid of the MATLAB simulation model. The results showed that the HRA has the capability to provide inherent fault-tolerance. Hence, the sudden failure of the system in the presence of fault was avoided. However, the capability of the actuator was found to be reduced gradually depending upon the number of faults.

Introduction

Faulty elements in any engineering system can be a huge hassle. Sometimes, they might cause irrevocable damage to the industries. Particularly, a fault in the safety-critical system can lead to disasters of unimaginable magnitude. So, designing modern engineering systems with a high level of reliability is of utmost importance to avoid any unexpected failures [1]. One important way this can be prevented is by having a fault-tolerance design that can tolerate any malfunctions of the individual components of the system. In general, fault-tolerance can be achieved by adopting a redundancy technique which includes the addition of resources, time or information beyond the normal requirements of the system being operated. In recent years, fault-tolerance has become one of the greatest tools for providing safety to any mechatronic system. The aircraft actuation and nuclear power systems are some of the most important systems that need redundancy to ensure reliability [2]. More recently, the aerospace field significantly increased the use of multi redundant electrical actuation systems to avoid unexpected failures [3,4]. However, in the case of nuclear power systems, hardware redundancy is introduced to confirm a high level of reliability of the control system [5]. Traditionally, the fault-tolerance for the actuation system is attained by connecting two or more identical actuators in parallel and the task to be completed by this group of actuators in parallel, is carried out by any one of the individual actuators from the same group. The fact that each of these actuators has the capability to perform the required task alone enables them to override any faulty actuators [6]. However, these actuators in parallel increases the weight and cost of the system and eventually, reduces the efficiency of the system. Moreover, the use of pure parallel configuration holds no value in the event of jamming/lock-up of an actuator within it.

1- Introduction

2- Preliminaries

3- Fault tolerant framework for NCS

4- Experimental results

5- Conclusion

References

Abstract

In recent years, neuromorphic computing systems (NCS) based on memristive crossbar have provided a promising solution to enable acceleration of neural networks. However, Stuck-at faults in the memristor devices significantly degrade the computing accuracy of NCS. In this paper, we propose an effective fault tolerant framework for memristive crossbar-based neuromorphic computing systems. First, a fault tolerance-aware hierarchical clustering method is proposed to partition weight connections of a sparse neural network into clusters. Then, for each cluster, memristive crossbar configuration is proposed to determine a suitable size of the crossbar with consideration of both hardware cost and successful mapping rate. Next, an integer linear programming formulation is developed to derive a connection-memristor mapping for fault tolerance. Finally, an efficient matching-based heuristic algorithm is further proposed to speed-up the fault-tolerant mapping process. Experimental results show that the proposed fault tolerant framework can improve the successful mapping rate and simultaneously reduce the hardware cost.

Introduction

Neuromorphic computing systems (NCS) based on hardware designs intend to mimic neuro-biological architectures [1]. Different from conventional von Neumann architectures, NCS is often constructed with highly parallel, extensively connected, and collocated computing and storage units, which eliminates the gap between CPU computing capacity and memory bandwidth [2]. However, the implementation of NCS on CMOS technology has been shown to suffer from mismatch between NCS building blocks (neuron and synapse) and CMOS primitives (Boolean logic). To address this problem, the emerging memristive technology is adopted to implement synapse circuit due to the similarity between memristive and synaptic behaviors [3,4]. For example, the memristor is suitable to store the weight of synapse since the resistance of memristor can be programmed by applying current or voltage. In addition, compared with the stateof-the-art CMOS design, memristive crossbar has been proven as one of the most efficient nanostructures that carry out matrix-vector multiplications while hardware cost and computation energy are significantly reduced [1]. However, despite of these tremendous advantages, NCS implementations on memristive crossbars also encounter some design challenges.

1- Introduction

2- Innovative transformations and fictitious machine

3- Control scheme in degraded operation mode

4- Innovative approach proof of concept

5- Conclusion and perspectives

References

Abstract

This paper deals with a control principle designed to allow remedial strategies for Permanent Magnet Synchronous Motor (PMSM) drives. The scope of the paper is focused on three-phase machines and it aims to present a simple and easy to tune control scheme for the system while it operates in degraded mode, namely when only two out of the three phases are operational. Compared to existing control strategy dedicated to degraded mode, this work proposes an innovative one using new reference frames. Based on two innovative transformations applied respectively to the currents and the voltages of the system, the proposed control scheme allows, in degraded mode, the decoupling control of the states of the system and leads to continuous controller references during system steady states. These properties lead to a very straightforward control scheme based on independent PI controllers and to high static and dynamic performances. The parameters setting of the controller is quite simple whatever the degree of magnetic coupling between the two remaining motor phases. A laboratory test bench has been built to establish a proof of concept of the suggested remedial strategy. It is based on a three-phase open-end-winding permanent magnet machine fed with a power inverter made of three full H-bridge. This experimental setup enables to validate the main operations of the ac motor drive under degraded mode operation: torque control, speed change. Switching between healthy mode and faulty mode is also performed successfully using this setup.

Introduction

Electric motor drives are often used for key functionalities which are mission critical and cannot tolerate any unexpected periods of downtime due to a failure. Examples include many manufacturing processes [13,23] and transport applications [31]. For instance power-assisted steering of a ground vehicle [3,26] or the actuators of the control surfaces of a plane [33] are key examples. Some of these applications call for demanding specifications regarding high power density and high efficiency. In such cases, the best choice is often a permanent magnet synchronous machine [29]. This constraint is frequently associated with embedded systems and usually coincides with a requirement for a high level of availability and reliability.

I- Introduction

II- Principle of Operation

III- Open-Circuit Fault Analysis

IV- Fault-Diagnosis and Post-Fault Operation

V- Simulation Results

VI- Conclusion

References

Abstract

Due to several advantages, three-phase Dual Active Bridge (DAB) converter is widely used in numerous applications nowadays. On the other hand, this converter is very vulnerable to Transistor Open-Circuit Fault (TOCF). Therefore, a faulttolerant (FT) scheme has been proposed in this paper to solve the problem. First, normal and faulty conditions are investigated, and according to the results, a fault-diagnosis (FD) approach is introduced. Using the outcomes of FD unit, a new post-fault strategy is proposed for the converter. The FD method is based on the DC component of transformer phase currents, and the basis of FT technique is shedding the faulty phase. Some benefits of the proposed scheme are preventing the shut-down of the system, no overvoltage or overcurrent, no additional power components, and insensitivity to operational conditions. Simulation results are also provided to confirm the analyses, and evaluate the performance of the proposed scheme.

INTRODUCTION

Power electronic converters are used in many industries such as renewable energy systems, transportation, and aerospace. All these industries are striving to improve the reliability of the systems with cost-effective solutions. Additionally, apart from the human safety risks, failures in converters may lead to economic loss as a result of stoppage of the system as well as maintenance costs. As a solution for the problem, Fault-Tolerant (FT) converters have been proposed and become a wide research area in recent literature [1]. FT converters are proposed for a variety of applications, including an AC-AC converter [2], a multi-level converter in [3] and a quasi-Z-source inverter in [4]. Fault-Diagnosis (FD) techniques are the main part of the FT converters, which usually can identify the location of the fault [5]. Many FD methods are proposed for semiconductor faults [1]. Generally, after the detection of the fault, several post-fault strategies can be employed to guarantee the continuity of system operation in spite of the failure. Some of these strategies are as follows: redundancy, reconfiguration, and soft shutdown. Furthermore, according to a survey about failed power converters, the most vulnerable components of a converter are power semiconductors. It is important to note that semiconductor faults account for 31% of failures in converter systems [1]. These faults are categorized into two main groups, including, short-circuit (SC) and open-circuit (OC) faults [1]. If not dealt with properly, both types can lead to serious damages. Typically, sufficient mechanisms are embedded in gate-drivers and power converters for SC protection. Unlike the SC fault, an OC fault usually remains undetected for a long time, deteriorating the performance of the system and can damage all the components. In addition, an OC fault in a power converter can occur as a result of the switch failure or a driver breakdown and it accounts for a large percent of semiconductor failures [6]. In addition, Dual Active Bridge (DAB), thanks to its numerous advantages, is extensively used in numerous applications. This converter has the benefits of high-power density, bidirectional power transfer, galvanic isolation, and so forth. All these benefits have paved the way for the usage of DAB in several applications, namely, electric vehicle, highfrequency-link power conversion systems, and battery storage systems[7]. Additionally, three-phase topology of the converter is usually preferred, in terms of efficiency and power-density, in industrial applications [8]. Having a large number of power semiconductors besides the corresponding gate-drivers, has made three-phase DAB seriously vulnerable to the power semiconductor failure. Even if a TOCF occurs in only one transistor of the converter, damage to other components, including 11 healthy switches, and the shutdown of the system will be unavoidable. Therefore, devising FD and FT techniques for this converter is necessary, in order to mitigate the consequence of TOCF and ensure the service continuity. In [9], faults on DC buses are investigated and techniques for tackling this problem is proposed.

I- Introduction

II- Reliability Analysis and its Improvement

III- Evaluation Platform and Experimental System

IV- Reliability Analysis and Experimental Evaluation

V- Conclusions and Future Research

References

Abstract

The reliability of safety-critical systems is very important especially in case of electronic systems which are working in environment with increased occurrence of faults. As an example, space, aerospace or medical systems can serve. Fault tolerance is one of the techniques the goal of which is to avoid the impact of faults on such systems. Lots of fault tolerance techniques exists and new ones are under investigation. This paper is targeted mainly to Field Programmable Gate Arrays (FPGAs) which are also the target technology of many fault tolerant techniques. It is important to evaluate and test these techniques. This paper is the continuation of our previously published research results which presents experimental approach to evaluate such fault tolerance techniques by monitoring the impact of faults in the experimental electro-mechanical system utilizing robot navigation in a maze. However, in this paper, we research and compare similarities of the theoretical estimation to various methods of the SEU injection approaches. The theoretical estimation is calculated using known equations. The impact of artificially faults injected into the electronic controller, in which Triple Modular Redundancy is applied, is monitored and used for statistic reliability analysis. This approach serves as a tool for the fast reliability evaluation during the development process of fault tolerance systems.

INTRODUCTION

The reliability of safety-critical electronic systems which are working in environment with increased occurrence of faults is a very challenging topic. A technique called fault tolerance [1] is commonly used technique which makes electronic systems more reliable. The goal of this approach is to keep the system functional, even in the presence of faults. It means that fault tolerance accepts the fact a fault can appear in electronic system. Various types of redundancy are the core of such techniques. Hardware and time redundancy are the most common ones. Combination and improvements of these basic methods are still under investigation, e.g. authors of [2] present approach which is based on the combination of hardware and time redundancies. Many fault-tolerant methodologies targeted to Field Programmable Gate Arrays (FPGAs) have been developed and new ones are under investigation [3]. The main reason is that FPGAs are more popular thanks to their flexibility and ability to be reconfigured in case of fault occurrence. Sensitivity of FPGAs to faults caused by charged particles [4] is the problem from the reliability point of view. The configuration of FPGA is stored as a bitstream in SRAM memory and charged particle can cause inversion of bit in the bitstream. This event is called Single Event Upset (SEU) [5].

Abstract

This paper presents a reconfigurable fault tolerant routing for Networks-on-Chip organized into hierarchical units. In case of link faults or failure of switches, the proposed approach enables the online adaptation of routing locally within each unit while deadlock freedom is globally ensured in the network. Experimental results of our approach for a 16 × 16 network show a speedup by a factor of almost four for routing reconfiguration compared to the state-of-the-art approach. Evaluation with transient faults shows that a dedicated reconfiguration unit enables successful reconfiguration of routing tables even in case of high error probabilities.

Introduction

The ongoing technology scaling allows an increasing number of cores to be implemented on a single chip, e.g. Intel’s Xeon Phi Coprocessor [1] or Tilera’s Tile-MX multicore processor [2]. As this scaling trend continues [3], future multiprocessor systems will feature hundreds of cores on a single chip.

The increasing size of on-chip systems poses a new challenge to Networks-on-Chip (NoCs).Mechanisms implemented in an NoC, such as table-based routing, work well for small systems but do not scale for bigger systems. A possibility to cope with scalability problems is the introduction of a hierarchical structure to NoCs. A hierarchical NoC can be obtained by constructing its topology using subnetworks or by segmenting a given topology into logical units. Both subnetworks and logical units enable formerly global mechanisms to be applied locally thus reducing their complexity. Compared to subnetworks, logical units have the advantage that they can be applied without changing an existing topology. Typically, network nodes (switch + core) are grouped into a logical unit if they are part of the same task and share a spatial relation.

The downside of technology scaling is the increased probability of occurrence of permanent faults in an NoC due to manufacturing inaccuracies [4] or wear-out effects such as electromigration [5] that emerge during system operation. The failure of links or switches due to permanent faults results in an altered network topology. In such a case, static routing can no longer maintain connectivity between system components. For this reason, it is crucial that the routing is adapted to the new network situation to enable packets to circumvent faulty components.