Abstract

I. Introduction

II. Three-Level Neutral Point Clamped Inverters

III. Proposed Neutral Point Clamped Inverters

IV. Operation of the Proposed Three-Level NPC Inverter

V. Comparison of the Proposed and Conventional Inverters

VI. Experimental Results

VII. Conclusion

References

Abstract

     The traditional neutral point clamped (NPC) inverter has short-circuit problem. The risk of short-circuit can be decreased by using dead-time in the switching signals. However, the dead-time decreases the achievable output voltage and causes distortion in the waveforms. To overcome the short-circuit problem, dual-buck NPC (DB-NPC) and split-inductor NPC (SI-NPC) inverters have been researched. However, the voltage stress of the two external diodes in the DB-NPC inverter is higher. On the other hand, the SI-NPC inverter has a problem of generating huge voltage spikes in the dead-time, which can destroy the semiconductor devices. In addition, the SI-NPC inverter cannot provide reactive power. This article presents a family of NPC inverters consisting of single-phase, three-phase, and cascaded inverters. The proposed inverters have no short-circuit and dead-time issues, therefore no high voltage and current spikes are caused. Also, the dead-time in the switching signals can be minimized. As a result, the magnitude of the output waveforms can be increased, and quality can be improved. Unlike the DB-NPC inverter, the voltage stress of all the semiconductor in the proposed inverter is lower, and unlike the SI-NPC inverter the proposed inverter provides reactive power. In this article, the proposed three-level NPC inverter is analyzed, designed, and tested. The voltage stress of the semiconductor devices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two external diodes is the source voltage. In addition to the aforementioned benefits, the proposed cascaded inverter reduces the total number of inductors. To verify the analysis, detailed simulation, and experimental results of the proposed three-level inverter with input voltage 640 V, output power 1.2 kW, and output voltage 220 Vrms are provided.

Introduction

     T HE traditional H-bridge inverter is shown in Fig. 1. The voltage stress on its switches is the input voltage Vdc. Therefore, the H-bridge inverter is well suitable for low-voltage applications. In high-voltage applications [1] such as HVdc transmission [2], large motor drive [3], locomotive [4], solid-state transformers [5], and reactive power compensation [6], the multilevel inverters are preferred. Flying capacitor [7], neutral point clamped (NPC) [8], and cascaded inverters [9], [10] are the famous multilevel inverter topologies.

     The flying capacitor inverters synthesize output voltage by adding voltages of the flying and dc-link capacitors. The NPC inverters synthesize output voltage by adding voltages of the dc-link capacitors. The cascaded inverters synthesize output voltage by adding voltages of the series-connected H-bridge cells. The cascaded inverters are highly modular and can reach a higher output voltage [11]. Also, they can bypass faulty cells [12]. The multilevel inverters have the advantages of lower switch voltage stress, lower switching losses, smaller output filter, better output waveforms, and lower electromagnetic interference (EMI) noise issues.

     The multilevel inverters are also getting popular in lowvoltage and low-power applications due to the possibility of obtaining lower common-mode voltage and higher efficiency over the H-bridge inverter. In [13], multilevel inverters have been discussed for the photovoltaic (PV) systems. In [14], a half-bridge three-level NPC inverter is compared with a halfbridge two-level inverter for PV applications. It is found in [14] that a lower leakage current and higher efficiency can be realized with the NPC inverter.

Conclusion

     This article presented new types of single-phase, three-phase, and cascaded NPC inverters. The proposed inverters have no short-circuit risk. The dead-time in the switching signals can be reduced. As a result, the distortion in the output waveforms can be decreased, higher switching frequencies can be used for the passive components size reduction and maximum available output voltage gain can be reached. Unlike the conventional SI-NPC inverters, the proposed inverters do not generate high-voltage spikes in the dead-time and provide reactive power. Unlike the DB-NPC inverters, the voltage stress of all the external diodes in the proposed inverter is lower. The proposed cascaded inverter inherits all the features of the proposed three-level inverter. In addition, it reduces the number of inductors by sharing the inductors between the cascaded units.

     A 1.2-kW hardware prototype was fabricated and tested with various loads at the input voltage 640 V, output voltage 110/220 Vrms, output power 1.2 kW, line-frequency 60 Hz, and switching frequency 30 kHz. The experimental results verified that the proposed inverter could generate good output waveforms, provide reactive power, works with dead and overlap-times, and obtains higher efficiency.

Abstract

1. INTRODUCTION

2. FIVE-LEVEL SWITCHED CAPACITOR INVERTER

3. MODULATION TECHNIQUE

4. PHOTOVOLTAIC APPLICATIONS OF THE SUGGESTED INVERTER

5. SIMULATION RESULTS

6. CONCLUSION

DISCLOSURE STATEMENT

REFERENCES

Abstract

     This paper proposes a switched-capacitor based single-phase five-level inverter configuration that operates under boost operation and generates a voltage that is more than the DC source voltage. The proposed five-level inverter uses a capacitor and boots the output voltage. In this proposed inverter, capacitor gets charged in parallel while it discharges in series connections so that output voltage may attain higher magnitude than the DC source voltage. Sinusoidal Pulse Width Modulation-based techniques are considered to produce the required gate pulses for operating the switching devices of the inverter. The five-level switched-capacitor inverter is combined with the PV system via DC–DC boost converters to extract the maximum power using MPPT algorithm. To verify its capability, the PV-based system is further integrated to the utility grid. The operation and performance of the suggested switched-capacitor inverter coupled with the grid-connected PV system are also analyzed by developing its model in MATLAB/Simulink environment.

Introduction

     Power electronic converters are getting evolved due to technological advancement in the design of power electronic devices as well as increase in its demand for more applications. The growth in demand for inverters has been observed because due to its application in the renewable energy source. The lesser costs of modern power electronics components make them useful for manufacturing and helping them to compete in the market. However, multi-level inverters use more switches; it is still economical to replace two-level inverters with MLIs because of several benefits such as lesser harmonic content, switching stress, and power losses [1–3]. Many scholars have paid attention to improve inverter topologies and their control methods. The lesser number of power electronics components used in multilevel inverters can further reduce the manufacturing cost [4–6]. The Cascaded H-bridge (CHB) inverter [7] and Neutral Point Clamped (NPC) inverter [8,9] are two standard multilevel inverters and having several industrial applications such as EV/HEV, HVDC, renewable energy sources, high-power motor drives, FACTs, STATCOM [10,11]. Several three-phase and single-phase MLI topologies of high voltage and medium power have been implemented for different applications [12,13]. A five-level inverter using two diodes, six switches, and two capacitors is proposed in [14].

CONCLUSION

     The proposed five-level switched-capacitor inverter topo logy for the PV application has been investigated in this paper. The developed single-phase switched-capacitor based inverter configuration consists of eight switching devices, only one DC source and one switched-capacitor. The inverter can produce five levels output voltage and the maximum amplitude can be twice the magnitude of DC voltage source. Moreover, it is also noticed that the charging as well as discharging of the switched-capacitor in the proposed multilevel inverter topology is symmetrical for both polarities of the output. Hence, the issue of capacitor voltage balancing is solved by using the switched capacitor of the suggested rating. The model of the recommended inverter-based grid-tied PV system is established in MATLAB/ Simulink environment and the performance of inverter under different modulation indexes is found satisfactory. The effectiveness of a grid-tied system was also investigated under different irradiance. Hence it can be resolved from the analysis that the proposed inverter is proficient for the application of a grid-tide PV system.

Abstract

1 Introduction

2 Proposed topology

3 Modulation and capacitance design

4 Comparison analysis and losses calculation

5 Simulation and experiment analysis

6 Conclusion

References

Abstract

     Multilevel inverters (MLIs) play an important role in research on renewable energy conversion. However, in traditional designs, the high-voltage stress of switching devices and the large number of switches limit the wide application of the inverter. To ameliorate these problems, this paper proposes a switched-capacitor multilevel inverter (SCMLI). When compared with traditional MLIs, the proposed SCMLI utilizes a switched-capacitor structure, where the capacitors can achieve voltage self-balancing without auxiliary methods. Thus, it permits changes of the positive and negative polarity of the output level without the need for an H-bridge. In addition, with the augment of the level in the expanded SCMLI structure, the maximum blocking voltage can be kept constant. To show the advantages of the proposed structure, an extensible single dc source five-level SCMLI prototype has been built. Through a comparative analysis with different topologies, this paper also presents the advantages of the proposed topology in terms of the output voltage gain, number of output levels, and voltage stress. Finally, the correctness and feasibility of the proposed inverter are validated by extensive experiments.

Introduction

     In recent years, multilevel inverters (MLIs) have become attractive converters in numerous applications such as renewable energy systems, motor drives, distributed generation systems, UPS systems, and fexible alternating current transmission system (FACTS) [1–3]. When compared with the traditional two-level inverters, MLIs have many advantages such as lower total harmonic distortion, reduced dv/ dt stresses, lower switching frequency, etc. [4]. In general, classic MLIs include neutral-point-clamped (NPC), fying capacitor (FC), and cascaded H-bridge (CHB) inverters. However, NPC and FC inverters employ a large number of clamping diodes and capacitors along with the increase of output levels, which inevitably raises the cost of topologies and the complexity of control strategies [5, 6]. Cascaded H-bridge MLIs have problems in terms of the lack of boost capacity and the need for multiple isolated dc sources [7, 8].

     To alleviate the problems of traditional MLIs, switchedcapacitor multilevel inverters (SCMLIs) have been proposed in [9–14]. SCMLIs can achieve multilevel output with a single dc source and fewer power devices. The fve-level inverter proposed in [9] uses only eight switches, but the topology contains two extra diodes and the working states for most of the switch pairs are inconsistent. In [10], a sevenlevel inverter with a single dc voltage source and 12 switches was proposed. Although the topology in [11] employs ten switches to output seven levels, there are still four extra diodes and ten gate drivers are required. The same issue can be found in [13], where the nine-level inverter can achieve twice voltage gain using many diodes and drivers. In addition, two capacitors are discharged for most of a cycle, which may bring about a large voltage ripple and the imbalance of capacitor voltage.

Conclusion

     This study presents an extensible single dc source fve-level MLI based on a switched-capacitor structure. The proposed MLI eliminates the need for H-bridge due to the inherent polarity reversal capability. In addition, the voltage of two capacitors can be self-balanced without any auxiliary circuits. Although ten switches are employed, only two switches have a voltage stress of 2Vdc, and only fve gate drivers are required, which signifcantly reduces the total voltage stress and cost of proposed inverter. In addition, the output levels and boosting factor can be raised by employing multiple switched-capacitor cells. Moreover, the maximum blocking voltage for all of the switches is kept within 2Vdc in the extended structure. A comparative study with other topologies showed that the proposed inverter has the advantages of reducing the TSV, the MBV, and the number of the power devices. Finally, the correctness and feasibility of the proposed multilevel inverter are validated through the simulation and experiment results obtained from a laboratory prototype.

Abstract

1. Introduction

2. PUC inverters

3. Microgrid

4. proportional–integral (PI) control of PUC inverters

5. MPC of PUC inverters

6. Simulation results

7. Hardware-in-loop (HIL) validations

8. Conclusions

Declaration of competing interest

References

Abstract

     In this paper, an outline of microgrid arrangements and control methods at various hierarchical levels of Packed U-Cell (PUC) converters are provided. The paper discusses the control of these topologies using various techniques. The goal of these control strategies is to maintain a small THD, superior steady-state, fast-dynamic response, and high-power factor while balancing capacitor voltages under different operating conditions. The PI current controller is modelled on five and seven-level PUC inverters. The PI voltage and current controllers have also been modelled on a seven-level PUC inverter. Thereafter, model predictive control of five, seven and fifteen level inverters are also formulated and then simulated using MATLAB/Simulink. Finally, HIL validation of different PUC inverters is performed.

Introduction

     The electrical power generated from renewable energy resources (solar, wind and hydro, etc.) are either used for domestic purposes directly or they are supplied to the grid [1]. For example, the power generated by a solar plant is of dc nature which is first conditioned and then inverted to get an alternating output. This ac power is then synchronized with the grid according to the grid’s characteristics (frequency and phase angles) [2]. In each of the steps, there are many parameters to be controlled in an accurate manner so that power quality is maintained. For this purpose, the most suitable consideration is the multi-level family converters.

     Due to improved power quality compared to their two-level counterparts in recent times, multilevel inverter (MLI) topology has become increasingly accepted in commercial applications. The reduced harmonic deformation, improved waveform like a sinusoidal waveform and enhanced use of switches due to diminished voltage stress. MLI have their uses in various fields of renewable energy sources including, HVDC, distributed generation (DG) system, application of industrial drive systems, uninterruptible power supplies, etc. [3], [4], [5], [6]. Based on a few semiconductor devices coupled with different dc links, MLIs generate sinusoidal waveforms at their outputs through staircase waveforms. MLI has traditionally been used in three major topologies in commercial applications within the last few decades: Cascade H-Bridge (CHB) inverters, Flying Capacitor (FC) inverters and Neutral Point Clamped (NPC) inverters. Each MLI topology, however, have some drawbacks, such as the increasing count of source necessities, the balancing of capacitor voltage, and the high necessity for switches counting in the CHB, FC, and NPC network topologies, respectively [3].

Conclusions

     The main purpose of this work is to present that MPC can be a better alternative to the classical PI control when applying such control techniques on different PUC topologies. Although MPC is known for its limitations in terms of the steady-state error, MPC can be one of the greatest alternatives to the classical PI due to the simplicity of designing this control, the ability to achieve multiple objectives, and the high accuracy in transient conditions.

     In this paper, MPC was successfully applied on five, seven and fifteen level PUC inverters and compared with PI control when applied on the same topologies. Although the converters’ voltages usually have higher THD when MPC is applied, the easy implementation of MPC and the capability to control more than one control variables are the some of the advantages which increase the chances of using MPC in such applications.

     In this work, using MPC, the capacitor voltages of the different PUC inverters were well regulated to follow their reference values using a single controller. However, in order to achieve similar performance using the classical PI control, two control loops, voltage and current control loops, were required to be designed which significantly increase the complexity of this control.

1- Introduction

2- Proposed system

3- Switching technique

4- Losses calculation

5- Simulation results

6- Experimental results

7- Conclusion

References

Abstract

A modified cascaded multilevel DC-AC converter using switched diodes is presented in this paper. This DC-AC converter produces great amount of voltage levels with minimized components by using hybrid modulation. It has two DC-AC converters coupled in cascade. First one is high frequency DC-AC converter and second one is low frequency DC-AC converter. The high frequency DC-AC converter is only capable to generate two levels with high frequency but the low frequency DC-AC converter is capable to produce great amount of voltage level by utilizing switched diodes. It reduces switching losses, size, cost and volume. Simulation of the circuit is done through MATLAB. The switching algorithm is realized by Spartan 6 FPGA processor board. Simulation outcomes are validated through experimental setup.

Introduction

As multi-level DC-AC converters have potential to generate waveforms with good harmonic range and voltage, they are getting increased attention. Many applications like AC power supplies, drive systems, power grid, and solar system uses multilevel DC-AC converter. The multilevel commences from three levels. Total Harmonic Distortion of the output waveform draws near to zero, if the amount of levels extent to infinity. One of the important favours of multilevel configuration is without curtailing the output power of DC-AC converter it can reduce harmonics in the output waveform. But, the issues like voltage unbalance, requirement of voltage clamping, circuit packaging and design constraints limit the attainable voltage level. Numerous traditional multilevel DC-AC converters is available out there. (i) Neutral Point Clamp (NPC) (ii) The Cascaded H-Bridge (CHB) (iii) The Flying Capacitor (FC) multilevel DC-AC converter [1]-[3]. Traditional multilevel DC-AC converters has unique demerits like high amount of switches for getting greater amount of output voltage levels that may demand excessive effort for the installation, the switching complexity, increased quantity of gate driver circuits and the size. Various multilevel DC-AC converter configurations brought together to curtail the switch count, gate drivers, dc sources and the voltage rating of the switches [4] – [9]. Quite a few control methods studied to curtail the harmonics in output [10]. Pulse Width Modulation (PWM) is broadly in a job to regulate the DCAC converter’s output.

An ever-increasing interest on integrating solar power to utility grid exists due to wide use of renewable energy sources and distributed generation. The grid-connected solar inverters that are the key devices interfacing solar power plant with utility play crucial role in this situation. Although three-phase inverters were industry standard in large photovoltaic (PV) power plant applications, the microgrid regulations increased the use of single-phase inverters in residential power plants and grid interconnection. This paper presents a detailed review on singlephase grid-connected solar inverters in terms of their improvements in circuit topologies and control methods. Even though there are many reviews have been proposed in the current literature, this study provides a differentiating approach by focusing on novel circuit topologies and control methods of string and micro inverters. The single and multi-stage solar inverters are reviewed in terms of emerging DC-DC converter and unfolding inverter topologies while the novel control methods of both stages have been surveyed in a comprehensive manner. The isolated and transformerless circuit topologies have been investigated by reviewing experimental and commercial devices. The soft computing, evolutionary and swarm intelligence based algorithms have been summarized in MPPT methods section while current injection and grid-connection control methods of unfolding inverters stage have been presented with and without PLL architecture. There are many papers have been compared and listed in each section to provide further outcomes which is followed by a summarizing discussion section and conclusion.

Introduction

The use of renewable energy sources (RESs) is increasing day by day in electricity generation due to their variety and support to utility grids. Besides the opportunities, the wide integrations of RESs to utility grid have brought several challenges in terms of planning, operating, maintenance and management issues. The distributed generation (DG) policies set by governments and demand side management (DSM) requirements of distribution system operators (DSOs) have leveraged the interoperability plans for generation plants including solar photovoltaics (PVs), wind turbines, fuel cells, and micro sources. A DG system comprised by various type of energy sources requires appropriate power electronic devices for power conversion for coupling at a single bus bar. The grid-connected inverters which are required for RES and DG integration to utility play crucial role in resource management. Moreover, the DC-DC converters are also required for regulating the DC power generated by PV or fuel cell sources while inverters are interfacing the entire power plant with grid (Kabalci, 2015; Kabalci and Kabalci, 2018, 2017). The microgrid applications have promoted efficient power conversion requirements especially in low-voltage range (Schweizer and Kolar, 2013) where the wide variety of power converter studies on DC-DC converters and cascaded multilevel inverters have been proposed in the literature. The PV power plants hold the biggest share by increasing their installed capacity up to 400 GWp by the end of 2017 which is estimated to tackle 1000 GWp capacity by 2022 (JaegerWaldau, 2017; Masson et al., 2018; Schmela, 2018). The total installed capacity of global PV power plants has been increased more than 100 GWp in 2017 as seen in Fig. 1. The main contribution is supported by subsidies provided by US and European governments.

I- Introduction

II- Improved t-type three-level inverter

III- Grid system mathematical model

IV- Model predictive direct power control strategy

V- Simulation and experiment

VI- Conclusion

References

Abstract

In this paper, the improved T-type three-level topology can significantly reduce the conduction loss in zero states compared with the traditional T-type three-level topology. In the DQ rotating coordinate system, a control method combining the model predictive algorithm and the direct power control is proposed. This control method divides 27 kinds of switch states into two groupsand decides which group of switch states is to be scrolled optimally by comparing the two capacitor voltages on the DC side. This method reduces the computational burden by reducing the number of rolling optimization under the condition of ensuring the neutral point voltage balance. Compared with the traditional multilevel model predictive control, the method eliminates the need of predicting the neutral point voltage as well as the cost function computation, and the control method is more direct and effective. Simulation and experimental results show that the proposed model predictive direct power control (MPDPC) method based on the improved T-topology can improve system robustness, fast dynamic response, wide operating range and stability.

Introduction

The inverter is a key part of the grid-connected system. It has high requirements on the quality and conversion efficiency of the waveform. A control method with good performance is very important. Improved T-type three-level inverter not only inherits the advantages of the traditional T-type three-level converter such as less component count,no clamping diodes through the current path,but also has more excellent performance in conduction loss. Compared with the traditional T-type three-level inverter topology, the improved T-type inverter reduces conduction losses by 90% under zero-vector conditions, which is equivalent to a total loss reduction of 30% [1]. MPC (Model Predictive Control) has the advantages of fast dynamic response, strong anti-interference ability, the low requirement on the model and the obvious advantages in dealing with nonlinear systems and multi-control targets. Ever since its inception, it has been constantly welcomed by industries system with strong disturbances and time-varying large inertia. It has been widely used in power electronics [2], motor-driven [3], solar wind power conversion [4],[5] and another control system. However, the traditional model predictive control increases dramatically as the number of levels increases and the number of control objectives increases. Direct power control has the advantages of good robustness, fast dynamic response, and a simple control structure. It has been widely used in practice. In this paper, the combination of model predictive control and direct power control not only inherits the advantages of good robustness of direct power control and simple control structure but also achieves the control of neutral point balance and constant power output.

I- Introduction

II- Finite-State Model Predictive Control

III- Proposed Finite-State Model Predictive Control With Integral Action

IV- Model Predictive Control in SP-ZSI

V- Experimental Results

VI- Conclusion

References

Abstract

Finite-State Model Predictive Control (FSCMPC) can be applied to a power converter if there is an accurate existing model of the converter. The best results will be achieved if and only if the parameters and variables that make up the system are properly estimated. If this is not the case, the predictions made using these strategies may be erroneous and cause problems, such as steadystate error with respect to the assigned desired references. This work presents a predictive control strategy with integral action that compensates for the differences between the estimated model and the inverter with the objective of achieving zero steady-state error without requiring external loops or state observers. The proposed strategy is tested on a single-phase Z-source inverter (SPZSI) so as to evaluate the error in both the ac and dc controlled variables with respect to their references to their cosigns. The experimental results confirm that the proposed strategy achieves zero error in steady state while maintaining the fast dynamic response of the classic predictive control.

Introduction

Model Predictive Control (MPC), despite having been under development for nearly forty years, is still considered an emerging strategy in many industrial applications [1]-[3]. In applications that use power converters, Finite-State Model Predictive Control (FCS-MPC) has received attention from researchers and developers for more than a decade [4]-[7]. This interest is due to the fact that defining the mathematical models to predict the behavior of the variables in a converter is not usually very complicated; furthermore, the existence of inexpensive, powerful digital signal processors (DSP) for the implementation of these strategies is an advantage that was not available 20 or 30 years ago [8]-[10]. Nowadays, in the specific field of static power converters, three-phase and single-phase inverters are fundamental in power integration applications for incorporating renewable energy to the distributed grid systems, micro-grids and/or isolated systems [11]-[17]. Diverse types of inverters have been controlled using FS-MPC’s. This strategy has been proposed in voltage source inverters (VSI), current source inverters (CSI) and also in Z-source inverter and quasi Z-source inverter (ZSI/qZSI) impedance networks [18]. Z-source inverters (ZSI/qZSI) are among the least-known inverters because they were first proposed less than 20 years ago [19]-[23]. These inverters have the advantage that they can behave as boosters or dampers on the ac-side, unlike VSIs, which can only act as dampers, or CSIs, which work as boosters [26][27]. This characteristic of Z-source inverters is considered a great advantage because it does not require the use of dc/dc converters to extend its operating ranges, which is a common practice with VSI’s and CSI’s.

1- Introduction

2- Generalized (3n+3) converter topology and operation

3- Generalized sinusoidal and non-sinusoidal PWM method

4- Particle swarm optimization for the optimal selection of sorting and offsetting

5- Simulation

6- Experimental results

7- Conclusion

References

Abstract

This paper presents a method to improve the power quality of a class of shared inverter topologies utilizing optimal sorting and the offsetting pulsewidth modulation (PWM) method. For the (3n+3)-switch converter topologies, a PWM procedure with two degrees of freedom is proposed to enhance the quality at the power side of the shared loads without adding more passive elements. Moreover, the two degrees of freedom are analyzed and optimized to improve the power quality of the output current of the shared loads. The optimization is achieved using particle swarm optimization (PSO) method in which three objective functions are formulated, each of which impacts the power quality at the shared load sides. The objective functions are: the total harmonic distortion (THD), the scaled total harmonic distortion (STHD), and the summation of the eleventh order of harmonics (SFEH) of the current of the shared loads. A case study that compares the PSO results with the conventional results is investigated to highlight the effectiveness of the proposed procedure. Furthermore, a test bed is built and the proposed procedure is experimentally investigated, verified, and compared to the simulation.

Introduction

Increasing the utilization of nonlinear loads in industry tools and household appliances that are driven by power electronics, and which produce harmonic currents, affects the power quality. Therefore, from a practical and industrial point of view, it is preferable to improve the quality of the power of the electrical load without increasing the cost, size, or complexity of the power electronics devices [1–3]. Harmonic mitigation can contribute in improving the power quality. Thus, many harmonic mitigation strategies have been proposed and implemented in the literature [4–7]. The main target of these studies was to maintain the total harmonic distortion (THD) of the phase current below a recommended level to avoid harmonic related problems. Although power quality improvement equipment such as passive filters [8], active filters [9], and hybrid filters [10,11] are commonly used to eliminate the harmonics, the use of such equipment may increase the size or cost of the system. On the other hand, different modulation techniques can be used to mitigate the harmonics [4–6]. To meet the power quality standards for cascaded H-bridge converter with variable DC-link, the authors in [12] employed an optimal selective harmonic reduction pulsewidth modulation (PWM) technique. Moreover, to improve the performance of a cascaded H-bridge multilevel active rectifier, the authors in [13] proposed a current reference based selective harmonic reduction PWM technique to satisfy current harmonic limits by analyzing and designing switching frequency and coupling inductance. A non-selective harmonic compensation method is introduced in [14] for a grid connected voltage source inverter (VSI), adopting a slide mode current harmonic controller. Due to the utilization of the sliding mode control theory, a fast-dynamic response with good disturbance rejection was achieved.

Based on the concept of switched-capacitor based multilevel inverter topology, a new structure for a boost multilevel inverter topology has been recommended in this paper. The proposed topology uses 11 unidirectional switches with a single switched capacitor unit to synthesize nine-level output voltage waveform. Apart from the twice voltage gain, self-voltage balancing of capacitor voltage without any auxiliary method along with reduced voltage stress has been the main advantages of this topology. The merits of proposed topology have been analyzed through various comparison parameters including component counts, voltage stresses, cost and efficiency with a maximum value of 98.3%, together with the integration of switched capacitors into the topology following recent development. Phase disposition pulse width modulation (PD-PWM) technique and nearest level control PWM (NLC-PWM) have been used for the control of switches. Different simulation and hardware results with different operating conditions are included in the paper to demonstrate the performance of the proposed topology.

Introduction

With the rapid growth of the renewable energy resources and its application in high voltage applications link industrial drive, high voltage dc transmission (HVDC), electric vehicle (EV), etc., power electronic converters play an important role in the power conversion suitable for each application. Multilevel inverters have its own importance in medium and high voltage applications due to reduced voltage rating of power semiconductor devices for high voltage generation, reduced harmonic contents, the small size of the filter, reduced EMI, improved efficiency and many more. Neutral point clamped (NPC), flying capacitor (FC) and cascade H-bridge (CHB) are traditional topologies that have been extensively researched and applied in different applications. However, the major concerns with these topologies have been the higher number of components, capacitor voltage balancing and complex control for a higher number of levels [1]–[4]. Therefore, numerous topologies have been proposed with reduce switch count [5]–[14]. In [7], an optimal design of multilevel inverter topology has been discussed. The topology of [7] uses several isolated dc voltage sources which restricts its applications. Another topology based on isolated voltage sources has been proposed in [9], in which 17 level output voltage has been achieved using four voltage sources. Similar topologies have been proposed in [10], [12]. In these topologies, higher number of levels can be generated to improve the quality of the output voltage. However, most of these topologies lack the voltage boosting ability.

The promising quasi-Z-Source inverter (qZSI) can regulate the DC-link voltage. In the study, a permanent magnet synchronous motor (PMSM) drive system is established with the qZSI. Based on the small-signal model, a feedback and feedforward compound control strategy is proposed and the dynamic performance of the converter is analyzed. The simulation and experimental results indicate that the compound control strategy effectively improves the static and dynamic characteristics of the DC-link voltage and reduces the influence of power variation on the DC-link voltage.

Introduction

A traditional motor drive system generally uses the battery plus voltage source inverter (VSI) to supply power [1], [2]. In order to raise the DC bus voltage, a cascaded DC-DC converter is often provided between the battery and the inverter [3]. In the system, the upper and lower switches of the same bridge arm cannot be turned on simultaneously. However, under complex working conditions, various disturbances may cause the switch mis-conduction and impair the reliability of the converter. To avoid the shoot-through state, it is necessary to add dead time, which brings out impulses in motor torque and harmonic loss increment and decreases the whole efficiency [4], [5]. The Z-Source inverter (ZSI) can function as both booster and inverter and replace the cascade system composed of the DC-DC converter and the VSI [6]. In addition, it can adjust the DC-link voltage and allow the shoot-through state. Compared with cascaded DC-DC systems, the ZSI is a single-stage system with higher reliability. However, it has the disadvantages of high voltage stress and discontinuous input current. Various impedance source inverters have been proposed. The trans-ZSI [7] and 0-ZSI [8] replace traditional ZSI inductors with double-winding transformer and reduce the number of capacitors to one. The trans-ZSI inverter maintains the high voltage boosting ability while ensuring the advantage of low voltage stress. With the increase in the shoot-through ratio, the voltage boosting ability of the 0-ZSI gradually decreases. T-ZSI [9] adopts the double-winding inductance coupling technology, which also reduces the numbers of inductors and capacitors to one.

I- Introduction

II- Inverter Design

III- Current Status

IV- Future Trends

V- Conclusions

References

Abstract

Traction inverters are crucial components of modern electrified automotive powertrains. Advances in power electronics have enabled lower cost inverters with high reliability, efficiency, and power density, suitable for mass market consumer automotive applications. This paper presents an independent review of the state-of-the-art traction inverter designs from several production vehicles across multiple manufacturers. Future trends in inverter design are identified based on industry examples and academic research. Wide bandgap devices and trends in device packaging are discussed along with active gate driver implementations, current and future trends in system integration, and advanced manufacturing techniques.

INTRODUCTION

ELECTRIFIED vehicles (EVs) are continuing to show promise as more manufacturers announce plans to develop electrified models in order to improve fuel economy and remain competitive as consumer demands shift towards efficient, cleaner vehicles. These include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), battery electric vehicles (BEVs), and fuel cell vehicles. At the heart of all electrified powertrains is one or more electric machines (EMs) which operate either in conjunction with an internal combustion engine (ICE) or replace it entirely. The EMs found in EVs today are most commonly of the AC permanent magnet (PM) or AC induction machine (IM) type [1, 2]. To drive them, a traction inverter is required to convert the direct current available from the battery pack to variable frequency alternating current. In addition to the motoring mode, the machines can also operate as generators, requiring the inverter to act as a rectifier and return energy to the battery.

I- Introduction

II- Analysis of Output Phase Angle

III- Simulation for Output Phase Angle

IV- Phase Synchronization Control

V- Prototype and Experimental Verification

VI- CONCLUSIONS

References

Abstract

In order to provide high and extendable power levels for inductive power transfer (IPT) system, a parallel multi-inverter system based on modular inverter is presented. Various power requirements can be implemented by an adjustment of the number of paralleled inverters, which provides a high modularity. A master-slave scheme is employed for the switching-driver signals of parallel inverters, where one acts as a leader while others act as followers. Despite the master-slave scheme, the proposed circuit topology has natural robustness because of the equality in terms of the hardware configuration of each modular inverter. For proper parameters, the output phase (current lagging corresponding voltage) of an inverter is lower than the average of output phase of all inverters, when its output voltage lags behind others, and vice versa. Based on this approach, PI controllers are designed to implement phase synchronization for output voltages of all inverters. An IPT prototype supplied by the proposed parallel multi-inverter with three inverters was designed, built, and tested. Experiments show that the proposed parallel multi-inverter system has not only good circulating current suppression capacity but also excellent performance of phase synchronization. The maximum dc-dc efficiency was 94% at a 35.1 kW receiving power. This paper is accompanied by a Matlab/Simulink file demonstrating phase synchronization control.

NTRODUCTION

To achieve high power levels while maintaining a high efficiency is a key requirement for many IPT applications, such as fast charging for high speed trains and for electrical vehicles [1]-[6]. Commonly, high power is shared by multiple inverters or invert-legs instead of a single inverter. Multilevel inverters [7], [8], input-series output-parallel (ISOP) inverters [9]-[11], and parallel multi-inverter system [12]-[21] are three typical topologies integrating the power from various inverters. The main issue of multilevel inverters for IPT is voltage-balance [7], [8]. The topology of multilevel inverters has an advantage of voltage stress reduction for semiconductor devices. However, it is hard maintain all inverters in phase at a high-switching frequency for IPT applications, which leads to a possible high voltage un-balance and therefore possible malfunction. Similarly, ISOP topology shares the input DC voltage equally among all inverters, which requires a high input DC voltage to provide high output power, and it is not reported for IPT applications [9]-[11]. With regard to parallel multi-inverter system, the main issue is current-balance [12]- [21]. The parallel multi-inverter topology shares the total current among various inverters while the current un-balance is suppressed by properly designed circulating-suppression controllers [12]-[20] or circuit topologies [21]. For the application of grid-connected inverters or un-interruptible power supply, current-balance controller is relatively easy to implemented because of the low operating frequency (i.e., 50 Hz) and resulting sampling speed requirement [12]-[18]. The droop control is a common algorithm for these 50 Hz applications. However, the current-balance controller is a bit difficult to implement for IPT applications, considering the influence of the high operating frequency on the sampling and the driver signal propagation delay. The literature [19] shows a design of a 3 kW experimental IPT using a parallel two-inverter topology, where a controller based on active and reactive currents decomposition is designed to minimize the circulating current among inverters. The literature [20] presents a parallel topology to integrate power from multiple inverters via transformers. The power sharing is obtained with a synchronous clamp-mode h-bridge control method. Because of the use of high-frequency transformers, the efficiency is dropped down.